The present invention relates to integrated circuits, and more particularly to chip interconnection and to forming contact pads on the back side of a semiconductor chip, and also to thinning of integrated circuits after circuit elements have been fabricated.
Some techniques for forming contacts on the chip "second" side are disclosed in U.S. Pat. No. 5,270,261 issued Dec. 14, 1993 to Bertin et al. and entitled "Three Dimensional Multichip Package Methods of Fabrication". Alternative techniques are desired.